NEPP Partners With NSWC Crane

3-minute read

The NASA Electronic Parts and Packaging (NEPP) Program has a long history of partnering with businesses and organizations to foster knowledge on radiation and reliability of new electronic devices and related technologies. It has partnered with the Naval Surface Warfare Center (NSWC) Crane Division (often referred to as Crane) for many years on different technologies.


NEPP and NSWC Crane members participate in a test for simulation of effects from Galactic Cosmic Ray (GCR) environment at Texas A&M University’s Cyclotron Institute. GCRs are highly energetic particles that pose a danger to electronics in many space missions. Credit: NEPP Program Co-Manager Ken LaBel .

Starting in Fiscal Year (FY) 2014, NEPP and NSWC Crane broadened their partnership with the following goals:

  • Identify devices and technologies of common interest
  • Coordinate test sample obtainment
  • Develop radiation and reliability test and analyses matrixes
  • Perform identified tests (individually and jointly)
  • Analyze and share data
  • Release as appropriate

Crane provides complementary expertise to the NEPP team with the joint goal of understanding the risks and strengths of emerging commercial technologies and potential applications to the harsh space environment.

Currently, the collaboration focuses on three device/technology areas that are of high interest to future military and space missions:

  • Advanced Complementary Metal-Oxide Semiconductor (CMOS) technology processors
  • Nonvolatile memories
  • Expansion to Field-Programmable Gate Arrays (FPGAs)

This particular effort developed from

  • Previous radiation test collaboration on Intel/Advanced Micro Devices Inc. microprocessors
  • NEPP management and Crane scientists and engineers’ desire to think outside the box and expand collaborations for the good of the military and aerospace community
  • The creation of the SPECTRA research group within NSWC Crane’s Flight Systems Division

This work started out as a standard task in which NASA brought a test set to NSWC Crane’s unique radiation exposure facility and the duo jointly irradiated samples and shared the data. This has been done previously with four earlier CMOS technology-node Intel parts. This time, however, NEPP and NSWC Crane decided to go further by utilizing multiple radiation test facilities and environments to more thoroughly explore the radiation sensitivities of this advanced and new technology.  

In addition, SPECTRA used its extensive failure analysis capabilities in both standard (imaging and construction) and novel (simulation and exposure) ways to augment the suite of radiation environment testing. The unique and superior skills on both sides resulted in both NEPP and NSWC Crane accomplishing well beyond what each might have individually.

The collaboration now has spanned five generations of Intel processor products, three Flash memory manufacturers and two novel resistive memories with planned inclusion on advanced FPGAs in FY17. (For more examples of this effort, see the references.)

One of the specific successes that stemmed from this collaboration was providing radiation performance data during the U.S. Department of State’s review of the International Traffic in Arms Regulations (ITAR). This data was a key demonstrator showing that changes to the ITAR were required and subsequently enacted in 2015.

NEPP and NSWC Crane are also currently collaborating on automotive-grade electronics evaluation. Building upon the success of these joint efforts has both teams enthusiastically looking forward to further collaborations, and they are discussing ways to extend the partnership even further.

For further information on this collaboration or discussion on access to NSWC Crane’s capabilities, please contact Ken LaBel.


[1] C. Szabo, A. R. Duncan, K. A. LaBel, M. J. Kay, P. Bruner, M. Krzesniak, L. Dong,  “Preliminary Radiation Testing of a State-of-the-Art Commercial 14nm CMOS Processor / System-on-a-Chip,” in Proc. 2015 IEEE Radiation Effects Data Workshop, Jul. 2015, pp. 1-8.

[2] K. A. LaBel, R. A. Gigliuto, C. M. Szabo, M. A. Carts, M. J. Kay, T. Sinclair, M. J. Gadlage, A. R. Duncan, J. D. Ingalls, “Hardness Assurance for Total Dose and Dose Rate Testing of a State-of-the-Art Off-Shore 32 nm CMOS Processor,” in Proc. 2013 IEEE Radiation Effects Data Workshop, Jul. 2013, pp. 1-6.

[3] A. R. Duncan, C.M. Szabo, D.P. Bossev, K.A. LaBel, A.M. Williams, M.J. Gadlage, J.D. Ingalls, C.H. Hedge, A.H. Roach, M. J. Kay, “Single Event Effects in 14-nm Intel Microprocessors,” Presented at 2016 IEEE Radiation Effects Data Workshop, Jul. 2016